LTC690 datasheet(5/16 Pages) LINER

5 / 16 page

LTC690/LTC691

LTC694/LTC695

VCC: 5V Supply Input. The VCC pin should be bypassed

with a 0.1

µF capacitor.

VOUT: Voltage Output for Backed Up Memory. Bypass with

a capacitor of 0.1

µF or greater. During normal operation,

VOUT obtains power from VCC through an NMOS power

switch, M1, which can deliver up to 50mA and has a typical

on resistance of 5

Ω. When VCC is lower than VBATT, VOUT

is internally switched to VBATT. If VOUT and VBATT are not

used, connect VOUT to VCC.

VBATT: Back-Up Battery Input. When VCC falls below VBATT,

auxiliary power, connected to VBATT, is delivered to VOUT

through PMOS switch, M2. If back-up battery or auxiliary

power is not used, VBATT should be connected to GND.

DAGRA

BLOCK

GND: Ground pin.

BATT ON: Battery On Logic Output from Comparator C2.

BATT ON goes low when VOUT is internally connected to

VCC. The output typically sinks 35mA and can provide base

drive for an external PNP transistor to increase the output

current above the 50mA rating of VOUT. BATT ON goes

high when VOUT is internally switched to VBATT.

PFI: Power Failure Input. PFI is the noninverting input to

the power-fail comparator, C3. The inverting input is

internally connected to a 1.3V reference. The power failure

output remains high when PFI is above 1.3V and goes low

when PFI is below 1.3V. Connect PFI to GND or VOUT when

C3 is not used.

PI FU CTIO S

CHARGE

PUMP

VBATT

VCC

CE IN

PFI

OSC IN

OSC SEL

WDI

RESET PULSE

GENERATOR

WATCHDOG

TIMER

RESET

BATT ON

VOUT

1.3V

GND

–

OSC

TRANSITION

DETECTOR

–

WDO

RESET

PFO

LOW LINE

CE OUT

690 BD

LTC690 데이터시트(PDF) 5 Page - Linear Technology

LTC690 데이터시트(HTML) 5 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

데이터시트 다운로드

링크 URL