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UPD78320 데이터시트(PDF) 39 Page - NEC |
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UPD78320 데이터시트(HTML) 39 Page - NEC |
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39 / 88 page ![]() Figure 3-6. Asynchronous Serial Interface Block Diagram BRGM BRG SCK SL CL PS0 PS1 RXE ASIM 2 1 Match Clear fCLK/8 fCLK/4 Send/Receive Baud Rate Generator Output Baud Rate Generator 16 1 16 1 INTSR Receive Control Parity Check Shift Register Receive Buffer RXD TXD RXB Shift Register OVE FE PE ASIS TXS Send Control Parity Addition Internal Bus INTST INTSER |
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