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M5-320/104-10VC 데이터시트(PDF) 2 Page - Lattice Semiconductor

부품명 M5-320/104-10VC
상세설명  Fifth Generation MACH Architecture
PDF  47 Pages
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제조업체  LATTICE [Lattice Semiconductor]
홈페이지  http://www.latticesemi.com
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M5-320/104-10VC 데이터시트(HTML) 2 Page - Lattice Semiconductor

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2
MACH 5 Family
Note:
1. “M5-xxx” is for 5-V devices. “M5LV-xxx” is for 3.3-V devices.
2. Preliminary specifications for new 6.5ns (Tpd) speed grade. 7.5ns speed grade in production now.
GENERAL DESCRIPTION
The MACH® 5 family consists of a broad range of high-density and high-I/O Complex
Programmable Logic Devices (CPLDs). The fifth-generation MACH architecture yields fast speeds
at high CPLD densities, low power, and supports additional features such as in-system
programmability, Boundary Scan testability, and advanced clocking options (Table 1). The MACH
5 family offers 5-V (M5-xxx) and 3.3-V (M5LV-xxx) operation.
Manufactured in state-of-the-art ISO 9000 qualified fabrication facilities on E2CMOS process
technologies, MACH 5 devices are available with pin-to-pin delays as fast as 5.5 ns (Table 2). The
5.5, 6.5, 7.5, 10, and 12-ns devices are compliant with the PCI Local Bus Specification.
Table 1. MACH 5 Device Features 1
Feature
M5-128/1
M5LV-128
M5-192/1
M5-256/1
M5LV-256
M5-320
M5LV-320
M5-384
M5LV-384
M5-512
M5LV-512
Supply Voltage (V)
5
3.3
5
5
3.3
5
3.3
5
3.3
5
3.3
Macrocells
128
128
192
256
256
320
320
384
384
512
512
Maximum User I/O Pins
120
120
120
160
160
192
192
160
192
256
256
tPD (ns)
5.5
5.5
5.5
5.5
5.5
6.52
6.52
6.52
6.52
6.52
6.52
tSS (ns)
3.0
3.0
3.0
3.0
3.0
3.02
3.02
3.02
3.02
3.02
3.02
tCOS (ns)
4.5
4.5
4.5
4.5
4.5
5.02
5.02
5.02
5.02
5.02
5.02
fCNT (MHz)
182
182
182
182
182
1672
1672
1672
1672
1672
1672
Typical Static Power (mA)
35
35
45
55
55
70
70
75
75
100
100
IEEE 1149.1 Boundary Scan Compliant
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PCI-Compliant
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes



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