DEVICES INCORPORATED

L2330

Coordinate Transformer

2

Special Arithmetic Functions

09/27/2001–LDS.2330-E

Configuration

0 0

No accumulation (normal operation)

0 1

PM accumulator path enabled

1 0

FM accumulator path enabled

1 1

Logical OR of PM and FM (Nonsensical)

SIGNAL DEFINITIONS

Power

+5V power supply. All pins must be

connected.

Clock

CLK — Master Clock

The rising edge of CLK strobes all

enabled registers.

Inputs

Data Input

x-coordinate/Polar Magnitude Data

rising edge of CLK.

Data Input

y-coordinate/Polar Phase Angle Data

input port. When RTP is HIGH, the input

accumulators should not be used. When

ACC is LOW, the upper 16 bits of YPIN

are the input port and the lower 16 bits

on the rising edge of CLK.

Outputs

Data Output

x-coordinate/Polar Magnitude Data

output port. When OERX is HIGH,

impedance state.

Data Output

y-coordinate/Polar Phase Angle Data

output port. When OEPY is HIGH,

impedance state.

Controls

ENXR — x-coordinate/Magnitude Data

Input Enable

When ENXR is HIGH, XRIN is latched

into the input register on the rising

edge of clock. When ENXR is LOW,

the value stored in the register is

unchanged.

Data Input Control

Phase Angle Data Input Control that

determines four modes as shown in

MC

0 0

Hold

Hold

0 1

Load

Hold

1 0

Hold

Load

1 1

Clear

Load

16

16

16

16

16

n

OVF

n

16

16

TRANSFORM

PROCESSOR

OERX

OEPY

TCXY

RTP

32

32

32

32

32

ENXR

2

*

REQUIRES 18 CYCLES TO COMPLETE AND IS FULLY PIPELINED

*

**

**

WHEN RTP IS HIGH ’n’ IS 16-BITS, WHEN RTP IS LOW ’n’ IS 24-BITS

**

AM

PM

FM

MC