LF2249 datasheet(3/8 Pages) LODEV

3 / 8 page

DEVICES INCORPORATED

LF2249

12 x 12-bit Digital Mixer

Video Imaging Products

08/16/2000–LDS.2249-J

ACC — Accumulator Control

The ACC input determines whether in-

ternal accumulation is performed on

the data input during the current clock

cycle. If ACC is LOW, no accumulation

is performed, the prior accumulated

sum is cleared, and the current sum of

products is output.

When ACC is

HIGH, the emerging products are

added to the sum of the previous prod-

ucts.

RND — Rounding Control

When RND is HIGH, the sum of the

products of the data being input on

the current clock cycle will be

rounded to 16 bits. To avoid the accu-

mulation of roundoff errors, round-

ing is only performed during the first

cycle of each accumulation process.

SWAP — Output Select

The SWAP control allows the user to

access all 24 bits of the accumulator

output by switching between upper

and lower 16-bit words. When SWAP

is HIGH, the upper 16 bits of the accu-

mulator are always output. When

SWAP is LOW, the lower 16 bits of the

accumulator are output on every

other clock cycle. As long as SWAP

remains LOW, new output data will

not be clocked into the output regis-

ters.

OE — Output Enable

When the OE signal is LOW, the

current data in the output registers

is available on the S15-0 pins. When

OE is HIGH, the outputs are in a

high-impedance state.

Outputs

S15-0 — Data Output

The current 16-bit result is available

on the S15-0 outputs. The output data

may be either the upper or lower 16

bits of the accumulator output, de-

pending on the state of SWAP. The

LSB is S0 (Figure 1b).

Controls

ENA–END — Pipeline Register Enable

Input data in the N (N = A, B, C, or D)

input register is latched into the corre-

sponding pipeline register stack on

each rising edge of CLK for which ENN

is LOW. Data already in the N register

stack is pushed down one register posi-

tion. When ENN is HIGH, the data in

the N pipeline register stack does not

change, and the data in the N input

stack.

ADEL3-0–DDEL3-0 — Pipeline Delay

Select

DEL (N = A, B, C, or D) is the 4-bit

registered pipeline delay select word.

DEL determines which stage of the N

pipeline register stack is routed to the

multiplier inputs. The minimum delay

is one clock cycle (NDEL = 0000), and

the maximum delay is 16 clock cycle

(NDEL = 1111). Upon power up, the

values of ADEL–DDEL and the con-

tents of the pipeline register stacks are

unknown and must be initialized by the

user.

NEG1–NEG2 — Negate Control

The NEG1 and NEG2 controls deter-

mine whether a subtraction or accumu-

lation of products is performed. When

NEG1 is HIGH, the product A x B is

negated, causing the product to be sub-

tracted from the accumulator contents.

Likewise, when NEG2 is HIGH, the

product C x D is negated, causing the

product to be subtracted as well. NEG1

and NEG2 determine the operation to

be performed on the data input during

the current clock cycle when ADEL–

DDEL = 0000.

CASEN — Cascade Enable

When CASEN is LOW, data being in-

put on the CAS15-0 inputs during that

clock cycle will be registered and accu-

mulated internally. When CASEN is

HIGH, the CAS15-0 inputs are ignored.

FT — Feedthrough Control

When FT is LOW and ADEL–DDEL =

0000, data being input on the CAS15-0

inputs is delayed three clock cycles to

align the data with the data being input

on the A11-0–D11-0 inputs. When FT is

HIGH, the cascade data being input is

routed around the three delay registers

to simplify the cascading of multiple

devices.

LF2249 데이터시트(PDF) 3 Page - LOGIC Devices Incorporated

LF2249 데이터시트(HTML) 3 Page - LOGIC Devices Incorporated

Html Pages

1 2 3 4 5 6 7 8

데이터시트 다운로드

링크 URL