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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LSH33 데이터시트(PDF) 2 Page - LOGIC Devices Incorporated |
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LSH33 데이터시트(HTML) 2 Page - LOGIC Devices Incorporated |
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2 / 8 page  08/16/2000–LDS.33-O 2 Special Arithmetic Functions DEVICES INCORPORATED LSH33 32-bit Barrel Shifter with Registers TABLE 1. WRAP MODE SHIFT CODE DEFINITIONS Shift Code Shift Code Shift Code Shift Code Shift Code Y Y Y Y Y31 31 31 31 31 Y Y Y Y Y30 30 30 30 30 Y Y Y Y Y29 29 29 29 29 ••• ••• ••• ••• ••• Y Y Y Y Y 16 16 16 16 16 Y Y Y Y Y 15 15 15 15 15 ••• Y Y Y Y Y2 2 2 2 2 Y Y Y Y Y1 1 1 1 1 Y Y Y Y Y0 0 0 0 0 00000 I31 I30 I29 ••• I16 I15 ••• I2 I1 I0 00001 I30 I29 I28 ••• I15 I14 ••• I1 I0 I31 00010 I29 I28 I27 ••• I14 I13 ••• I0 I31 I30 00011 I28 I27 I26 ••• I13 I12 ••• I31 I30 I29 • ••• •••• • ••• ••• • ••• •••• • ••• ••• • ••• •••• • ••• ••• 01111 I16 I15 I14 ••• I1 I0••• I19 I18 I17 10000 I15 I14 I13 ••• I0 I31 ••• I18 I17 I16 10001 I14 I13 I12 ••• I31 I30 ••• I17 I16 I15 10010 I13 I12 I11 ••• I30 I29 ••• I16 I15 I14 • ••• •••• • ••• ••• • ••• •••• • ••• ••• • ••• •••• • ••• ••• 11100 I3 I2 I1••• I20 I19 ••• I6 I5 I4 11101 I2 I1 I0••• I19 I18 ••• I5 I4 I3 11110 I1 I0 I31 ••• I18 I17 ••• I4 I3 I2 11111 I0 I31 I30 ••• I17 I16 ••• I3 I2 I1 TABLE 2. FILL MODE SHIFT CODE DEFINITIONS — LEFT SHIFT In fill mode, as in wrap mode, the shift code input represents the number of shift positions directly for left shifts, but the two’s complement of the shift code results in the equivalent right shift. However, for fill mode the R/L input can be viewed as the most significant bit of a 6-bit two’s comple- ment shift code, comprised of R/L concatenated with the SI4–SI0 lines. Thus, a positive shift code (R/L = 0) results in a left shift of 0–31 positions, and a negative code (R/L = 1) a right shift of up to 32 positions. The LSH33 can thus effectively select any contigu- ous 32-bit field out of a (sign extended and zero filled) 96-bit "input." OUTPUT MULTIPLEXER The shift array outputs can be regis- tered and then applied to a 2:1 multi- plexer controlled by the MS/LS select line. This multiplexer makes available at the output pins either the most significant or least significant 16 outputs of the shift array. PRIORITY ENCODER The 32-bit input bus drives a priority encoder which is used to determine the first significant position for purposes of normalization. The priority encoder produces a five-bit code representing the location of the first non-zero bit in the input word. Code assignment is such that the priority encoder output represents the number of shift positions required to left align the first non-zero bit of the input word. Prior to the priority encoder, the input bits are individu- ally exclusive OR’ed with the SIGN input. This allows normalization in floating point systems using two’s complement mantissa representation. A negative value in two’s complement representation will cause the exclusive OR gates to invert the input data to the encoder. As a result, the leading significant digit will always be "1." Shift Code Shift Code Shift Code Shift Code Shift Code Y Y Y Y Y31 31 31 31 31 Y Y Y Y Y30 30 30 30 30 Y Y Y Y Y29 29 29 29 29 ••• ••• ••• ••• ••• Y Y Y Y Y 16 16 16 16 16 Y Y Y Y Y 15 15 15 15 15 ••• Y Y Y Y Y2 2 2 2 2 Y Y Y Y Y1 1 1 1 1 Y Y Y Y Y0 0 0 0 0 00000 I31 I30 I29 ••• I16 I15 ••• I2 I1 I0 00001 I30 I29 I28 ••• I15 I14 ••• I1 I0 0 00010 I29 I28 I27 ••• I14 I13 ••• I0 00 00011 I28 I27 I26 ••• I13 I12 ••• 000 • ••• •••• • ••• ••• • ••• •••• • ••• ••• • ••• •••• • ••• ••• 01111 I16 I15 I14 ••• I1 I0••• 000 10000 I15 I14 I13 ••• I0 0 ••• 000 10001 I14 I13 I12 ••• 00 ••• 000 10010 I13 I12 I11 ••• 00 ••• 000 • ••• •••• • ••• ••• • ••• •••• • ••• ••• • ••• •••• • ••• ••• 11100 I3 I2 I1••• 00 ••• 000 11101 I2 I1 I0••• 00 ••• 000 11110 I1 I0 0 ••• 00 ••• 000 11111 I0 00 ••• 00 ••• 000 |
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