UPD98405 datasheet(21/64 Pages) NEC

21 / 64 page

Data Sheet S12689EJ2V0DS00

µµµµPD98405

1.5 JTAG Boundary Scan Signals

Remark This function can be supported upon request.

These signals conform to IEEE1149.1 JTAG Boundary-Scan Standard.

Pin Name

Pin No.

I/O

I/O Level

Function

JDI

285

TTL

Boundary scan data input.

Connect this pin to ground when it is not used.

JDO

284

3-state

TTL

Boundary scan data output.

Open this pin when it is not used.

JMS

283

TTL

Boundary scan mode select.

Connect this pin to ground when it is not used.

JCK

282

TTL

Boundary scan clock input.

Connect this pin to ground when it is not used.

JRST_B

281

TTL

Boundary scan reset.

Connect this pin to ground when it is not used.

1.6 Other Signals

Pin Name

Pin No.

I/O

I/O Level

Function

SCLK

198

TTL

SAR system clock.

This pin supplies a clock for a SAR block operation.

The maximum clock frequency is 25 MHz.

PCI_MODE

118

TTL

PCI/generic bus mode.

This pin selects PCI or generic bus mode.

0: Generic bus mode

1: PCI bus mode

TEST

271

TTL

Internal test pin.

Open this pin. When a high level is input to this pin, the test

mode is selected.

This signal is internally pulled down.

The test mode is used for internal testing and cannot be used by

the user.

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