RT9705B datasheet(7/12 Pages) RICHTEK

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RT9705B

DS9705B-03 April 2011

www.richtek.com

Note 1.

Stresses listed as the above “Absolute Maximum

Ratings” may cause permanent damage to the

device. These are for stress ratings. Functional

operation of the device at these or any other

conditions beyond those indicated in the operational

sections of the specifications is not implied.

Exposure to absolute maximum rating conditions

for extended periods may remain possibility to affect

device reliability.

Note 2.

θJA is measured in the natural convection at

TA = 25

°C on a low effective thermal conductivity test

board of JEDEC 51-3 thermal measurement

standard.

Note 3.

Devices are ESD sensitive. Handling precaution

recommended.

Note 4.

The device is not guaranteed to function outside its

operating conditions.

Note 5.

Performance at

−5°C ≤ TA ≤ 85°C is assured by

design.

Note 6.

Not tested for production.

Note 7.

The UVLO is without latch. In VIN falling dege, the

output voltage will depend on IOUT and COUT. Please

see below curve as reference.

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Power Switch Timing (Note 6)

Output Rise Time from

an enable

VIN1 = VIN2 = 3.3V, IOUT = 500mA

See Timing Diagram (a)

1.72

Output Fall Time from a

disable

VIN1 = VIN2 = 3.3V, IOUT = 500mA

See Timing Diagram (a)

0.1

0.26

1.5

VIN1 to VIN2 transition,

VIN1 = 3.3V, VIN2 = 5V

Transition Time

VIN2 to VIN1 transition,

VIN1 = 5V, VIN2 = 3.3V

IOUT = 500mA, (Measure

transition time as 10 to 90%

rise time or from 3.4V to

4.8V on VOUT) See Timing

Diagram (b)

μs

Turn-on Propagation

Delay from Enable

tPLH1

VIN1 = VIN2 = 3.3V, Measure from enable to 10% of

VOUT, IOUT = 500mA See Timing Diagram (a)

Turn-off Propagation

Delay from Disable

tPHL1

VIN1 = VIN2 = 3.3V, Measure from disable to 90% of

VOUT, IOUT = 500mA See Timing Diagram (a)

Switch-over Rising

Propagation Delay

tPLH2

Logic 1 to Logic 0 transition

on D1, Measure from D1 to

10% of VOUT

100

μs

Switch-over Falling

Propagation Delay

tPHL2

Logic 0 to Logic 1 transition

on D1, Measure from D1 to

90% of VOUT

VIN1 = 3.3V,

VIN2 = 5V,

VD0 = 0V,

IOUT = 500mA

See Timing Diagram (c)

3.8

VIN2 = 2.2V, COUT = 10uF, RL = 180

VOUT Response vs. UVLO

Time (1ms/Div)

VOUT

(1V/Div)

VIN1

(1V/Div)

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