전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

RFAC3612 데이터시트(PDF) 10 Page - RF Micro Devices

부품명 RFAC3612
상세설명  3 Wire SPI Compatible Control
PDF  15 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  RFMD [RF Micro Devices]
홈페이지  http://www.rfmd.com
Logo RFMD - RF Micro Devices

RFAC3612 데이터시트(HTML) 10 Page - RF Micro Devices

Back Button RFAC3612 Datasheet HTML 6Page - RF Micro Devices RFAC3612 Datasheet HTML 7Page - RF Micro Devices RFAC3612 Datasheet HTML 8Page - RF Micro Devices RFAC3612 Datasheet HTML 9Page - RF Micro Devices RFAC3612 Datasheet HTML 10Page - RF Micro Devices RFAC3612 Datasheet HTML 11Page - RF Micro Devices RFAC3612 Datasheet HTML 12Page - RF Micro Devices RFAC3612 Datasheet HTML 13Page - RF Micro Devices RFAC3612 Datasheet HTML 14Page - RF Micro Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 15 page
background image
RF Micro Devices Inc.
7628 Thorndike Road, Greensboro, NC 27409-9421
DS140530
For sales or technical support, contact RFMD at +1.336.678.5570 or customerservice@rfmd.com.
The information in this publication is believed to be accurate. However, no responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any infringement of patents or other rights of
third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent rights of RFMD. RFMD reserves the right to change component circuitry, recommended
application circuitry and specifications at any time without prior notice.
10 of 15
RFAC3612
Test Set-up
The RFAC3612 is controlled by a single direction 3-wire SPI compatible interface. The RFAC3612 has 3 logic input pins for:
SCLK: Serial Input, SDATA: Serial Data Input; CS: Chip Select
The serial master initiates the start of the telegram by driving the chip select signal CS low. Each bit in the 16-bit telegram is clocked in by
the slave on the falling edge of SCLK.
SDATA bits consist of 3 groups:
F0 to F7: are fixed bits, these do not change.
S0 to S1: controls the RF1 and RF2 shunt switches
D5 to D0: is the 6-bit data word, used for controlling the PAC. SDATA bits are clocked in the order shown below, with D5 being the first
bit. The PAC activates the clocked values of SDATA on the falling edge of SCLK of the 16
th bit.
MSB
LSB
F6
F5
F4
F2
F3
F7
SCLK
SDATA
CS
F1
F0
S1
D5
S0
D4
D3
D2
D0
D1
tSCLK
tSDATA_SCLK
tCS_SCLK
tSCLK_CS
tCSHIGH
tSDATA
A quick overview of the telegram bits is shown below.
Telegram Bits
Function and Description
F0-F7
8-bit set of fixed bits, must be set to 00100000
S1
Data bit S1, controls shunt switch on port RF2. 0 = shunt switch is Off, 1 = shunt switch is On. After power-up
the value of S1 is 0, i.e. shunt switch is Off.
S0
Data bit S0, controls shunt switch on port RF1. 0 = shunt switch is Off, 1 = shunt switch is On. After power-up
the value of S0 is 0, i.e. shunt switch is Off.
D0-D5
Data bit D0-D5, controls the state of PAC. (D5 is most significant bit, D0 is least significant bit). After power-
up the value of D0-D5 is 000000, i.e. state 0.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com