P4C1281/P4C1282 - ULTRA HIGH SPEED 64K x 4 CMOS STATIC RAMS

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Document # SRAM136 REV OR

AC TEST COnDITIOnS

TRUTH TABLE

P4C1281 (P4C1282)

Input Pulse Levels

GND to 3.0V

Input Rise and Fall Times

3ns

Input Timing Reference Level

1.5V

Output Timing Reference Level

1.5V

Output Load

See Figures 1 and 2

Mode

CE

WE

I/O

Power

Standby

H

x

High Z

Standby

Read

L

H

D

OUT

Active

Write

L

L

D

Active

Figure 1. Output Load

Figure 2. Thevenin Equivalent

* including scope and test fixture.

note:

Because of the ultra-high speed of the P4C1281 and P4C1282, care

must be taken when testing this device; an inadequate setup can cause

a normal functioning part to be rejected as faulty. Long high-inductance

leads that cause supply bounce must be avoided by bringing the V

CC

and ground planes directly up to the contactor fingers. A 0.01 µF high

frequency capacitor is also required between V

signalreflections,properterminationmustbeused;forexample,a50Ωtest

environment should be terminated into a 50Ω load with 1.73V (Thevenin

Voltage) at the comparator input, and a 116Ω resistor must be used in

series with D