Low-Power, 8-Channel,

Serial 12-Bit ADCs

16

______________________________________________________________________________________

Reference

Reference-

VREF

Power-

Power-Up

Maximum

Buffer

Buffer

Capacitor

Down

Delay

Sampling

Compensation

(µF)

Mode

(sec)

Rate (ksps)

Mode

Enabled

Internal

Fast

5µ

26

Enabled

Internal

Full

300µ

26

Enabled

External

4.7

Fast

See Figure 14c

133

Enabled

External

4.7

Full

See Figure 14c

133

Disabled

Fast

2µ

133

Disabled

Full

2µ

133

Table 5. Typical Power-Up Delay Times

PD1

PD0

Device Mode

1

1

External Clock Mode

1

0

Internal Clock Mode

0

1

Fast Power-Down Mode

0

0

Full Power-Down Mode

SHDN

Device

Reference-Buffer

State

Mode

Compensation

1

Enabled

Internal Compensation

Floating

Enabled

External Compensation

0

Full Power-Down

N/A

Table 6. Software Shutdown and Clock Mode

Table 7. Hard-Wired Shutdown and

Compensation Mode

POWERED UP

FULL

POWER

DOWN

POWERED

UP

POWERED UP

DATA VALID

(12 DATA BITS)

DATA VALID

(12 DATA BITS)

DATA INVALID

VALID

EXTERNAL

EXTERNAL

INTERNAL

SX XXXX 11

S

0 1

XX

X

X

X

X X XXX

S1 1

FAST

POWER-DOWN

MODE

DOUT

DIN

CLOCK

MODE

SHDN

SETS EXTERNAL

CLOCK MODE

SETS EXTERNAL

CLOCK MODE

SETS FAST

POWER-DOWN

MODE

Figure 12a. Timing Diagram Power-Down Modes, External Clock