REVISION A 07/17/15

3

2-OUTPUT 3.3V PCIE GEN 1-2-3 CLOCK GENERATOR

9FGL02 DATASHEET

Pin Descriptions

Pin#

Pin Name

Type

Pin Description

1

XIN/CLKIN_25

IN

Crystal input or Reference Clock input. Nominally 25MHz.

2

X2

OUT

Crystal output.

3

VDDXTAL3.3

PWR

Power supply for XTAL, nominal 3.3V

4

vSADR/REF3.3

LATCHED

I/O

Latch to select SMBus Address/3.3V LVCMOS copy of X1/REFIN pin

5

GNDREF

GND

Ground pin for the REF outputs.

6

GNDDIG

GND

Ground pin for digital circuitry

7

VDDDIG3.3

PWR

3.3V digital power (dirty power)

8

SCLK_3.3

IN

Clock pin of SMBus circuitry, 3.3V tolerant.

9

SDATA_3.3

I/O

Data pin for SMBus circuitry, 3.3V tolerant.

10

GND

GND

Ground pin.

11

VDD3.3

PWR

Power supply, nominal 3.3V

12

vOE0#

IN

Active low input for enabling DIF pair 0. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

13

DIF0

OUT

Differential true clock output

14

DIF0#

OUT

Differential Complementary clock output

15

GNDA

GND

Ground pin for the PLL core.

16

VDDA3.3

PWR

3.3V power for the PLL core.

17

DIF1

OUT

Differential true clock output

18

DIF1#

OUT

Differential Complementary clock output

19

vOE1#

IN

Active low input for enabling DIF pair 1. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

20

VDD3.3

PWR

Power supply, nominal 3.3V

21

GND

GND

Ground pin.

22

^CKPWRGD_PD#

IN

Input notifies device to sample latched inputs and start up on first high assertion.

Low enters Power Down Mode, subsequent high assertions exit Power Down

Mode. This pin has internal pull-up resistor.

23

vSS_EN_tri

LATCHED IN

Latched select input to select spread spectrum amount at initial power up :

1 = -0.5% spread, M = -0.25%, 0 = Spread Off

24

GNDXTAL

GND

GND for XTAL

25

ePAD

GND

Connect to ground