Data Sheet #: SG084

Page 2 of 14

Rev: 00

Date: 09/08/04

Features

Table 1

Parameter

Specifications

Notes

Input Logic

CMOS

Input Frequency Range

8 kHz - 176 MHz

Alarms

Active Low, Combined LOR/LOL

VCXO Output Logic Type

LVPECL (3x)

Reference Output Logic Type

CMOS (1x)

Package

FR4 SM 1.35" x 1.0" x 0.40"

General Description

The SCG52 Series is a dual input, phase locked loop

generating LVPECL outputs from an intrinsically low jitter

voltage controlled crystal oscillator. The LVPECL and

CMOS outputs may be disabled.

The unit has an acquisition time of about 1 second and

it is tolerant of different reference duty cycles.

Further features include a combined LOL/LOR alarm

output for Loss-of-Reference (LOR) and Loss-of-Lock

(LOL). When both references are lost , the SCG52 will

indicate an alarm and will automatically enter Free Run,

which will guarantee a 20 ppm accurate output. The

SCG52 will remain in Free Run until a valid reference

is detected on either input. Additionally the Free Run

mode may be entered manually.

The alarms and reference output may be put into

the tri-state high impedance condition for external

testing purposes.

The maximum package dimensions are 1.35” x 1.0”

x 0.40” on a 6 layer FR4 board with castellated pins.

Parts are assembled using high temperature solder to

withstand 63/37 alloy, 180° C surface mount reflow

processes.

Functional Block Diagram

Figure 1

Divider

Divider

Alarm

Detection

Analog

Filter

Free Run

Control

Buffer/

Divider

VCXO

Alarm Output

(Pin 1)

Reference A

(Pin 2)

Reference B

(Pin 4)

Control 2

(Pin 20)

Control 1

(Pin 19)

(Pin 11)

(Pin 12)

(Pin 9)

(Pin 10)

(Pin 5)

(Pin 6)

(Pin 15)

10 k

Ω

10 k

Ω

33

Ω