Preliminary Data Sheet #: SG053

Page 2 of 16

Rev: P01

Date: 08/05/02

General Description

The SCG4540 is a mixed-signal phase locked loop

generating LVPECL outputs from an intrinsically low

jitter, voltage controlled, crystal oscillator. The LVPECL

outputs may be disabled.

The SCG4540 can lock to one of two 10 kHz,

external references, which is selectable using the SEL

AB

input select pin. The unit has a fast acquisition time of

about 1 second and it is tolerant of different reference

duty cycles.

The SCG4540 includes an alarm output that

indicates deviations from normal operation. If a Loss-

of-Reference (LOR) or Loss-of-Lock (LOL) is detected

the alarm with indicate the need for a reference

rearrangement. If both references A and B are absent

the module will enter Free Run operation. The FR

status

pin will indicate that the module is in Free Run

operation. Frequency stability during Free Run

operation is guaranteed to ±20 ppm. Additionally the

Free Run mode may be entered manually.

The package dimensions are 1” x 1.025” x .45” on a

6 layer FR4 board with castellated pins. Parts are

assembled using high temperature solder to withstand

63/37 alloys, 180°C surface mount reflow processes.

Maximum Dimension Package Outline

Figure 1

Model Comparison Table

Table 1

Dual

Max

LVPECL

Model

Input

Duty

Oscillator Output

Notes

Ref Freq

Cycle

(Pins 16 & 18)

SCG4500

8 kHz/8 kHz

40/60

77.76 MHz,155.52 MHz,125 MHz

Basic Model

SCG4510

1.544 MHz/1.544 MHz

40/60

155.52 MHz

SCG4520

19.44 MHz/19.44 MHz

40/60

77.76 MHz,155.52 MHz

SCG4540

10 kHz/10 kHz

40/60

163.84 MHz

*Features which differentiate a model from the base model (SCG4500) are highlighted in boldface color and in the notes column.

Block Diagram

Figure 2

PHASE

ALIGNER

REFB

REFA

SEL AB

ANALOG

FILTER

Q

QN

1 / N

ALARM

LOW JITTER

VCXO

FREE RUN STATUS

OPTIONAL

REFERENCE

OUTPUT

FORCE

FREE RUN

ENABLE/

TRI-STATE

DPFD