Low-Voltage, Single-Supply

Dual SPST/SPDT Analog Switches

8

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GND

COM

V+

IN

OFF

ON

OFF

Q = (

NC

OR NO

IN DEPENDS ON SWITCH CONFIGURATION;

INPUT POLARITY DETERMINED BY SENSE OF SWITCH.

OFF

ON

OFF

IN

V+

IN_

MAX4541

MAX4542

MAX4543

MAX4544

Figure 4. Charge Injection

50%

0.9

+3V

0

0

LOGIC

INPUT

SWITCH

OUTPUT 2

0

0.9

LOGIC

INPUT

300

Ω

GND

NC2

IN2

IN1

NO1

V+

V+

35pF

+3V

300

Ω

35pF

COM1

COM2

SWITCH

OUTPUT 1

MAX4543

50%

+3V

0

LOGIC

INPUT

SWITCH

OUTPUT

0.9

LOGIC

INPUT

300

Ω

GND

NO

IN

NC

V+

V+

35pF

+3V

COM

MAX4544

Figure 3a. Break-Before-Make Interval (MAX4543 only)

Figure 3b. Break-Before-Make Interval (MAX4544 only)

_________________________________Test Circuits/Timing Diagrams (continued)