Low-Voltage, CMOS Analog

Multiplexers/Switches

12

______________________________________________________________________________________

50%

0V

0V

90%

90%

50%

0V

0V

90%

90%

50%

0V

90%

90%

GND

B

A

C

Enable

X0

X1–X7

X

MAX4581

300

Ω

50

Ω

35pF

GND

B

A

Enable

X0, Y0

X1–X3, Y1–Y3

X, Y

MAX4582

300

Ω

50

Ω

35pF

GND

A

B

C

Enable

X1, Y1, Z1

X0, Y0, Z0

X, Y, Z

MAX4583

300

Ω

35pF

50

Ω

TEST EACH SECTION INDIVIDUALLY.

Figure 3. Inhibit Switching Times

_________________________________Test Circuits/Timing Diagrams (continued)