Fast, Low-Voltage, Dual 4

Ω SPDT

CMOS Analog Switches

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7

tr < 5ns

tf < 5ns

50%

0

0

0.9

0.9

SWITCH

OUTPUT

LOGIC

INPUT

LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES

THAT HAVE THE OPPOSITE LOGIC SENSE.

MAX4635/MAX4636

LOGIC

INPUT

GND

NO_ or NC_

IN_

NC_ or NO_

V+

V+

COM_

Figure 1a. Switching Time

50%

0

LOGIC

INPUT

0.9

MAX4635/MAX4636

LOGIC

INPUT

GND

NO_ or NC_

IN_

NC_ or NO_

V+

V+

COM_

tr < 5ns

tf < 5ns

Figure 1b. Break-Before-Make Interval

GND

COM_

V+

IN

OFF

ON

OFF

Q = (

NC_

OR NO_

IN DEPENDS ON SWITCH CONFIGURATION;

INPUT POLARITY DETERMINED BY SENSE OF SWITCH.

OFF

ON

OFF

IN

V+

IN

MAX4635/MAX4636

Figure 2. Charge Injection