An additional 110µA of supply current can be saved

when the internal reference is not used by connecting

such as the 2N7002, can be used to turn off the internal

reference to create a shutdown mode with minimum

current drain (Figure 3). When CLR is high, the transis-

tor pulls REFGND to AGND and the reference and DAC

operate normally. When CLR goes low, REFGND is

same time, CLR resets the DAC register to all 0s, and

the op-amp output goes to 0V for unity-gain and

G = 2 modes. This reduces the total single-supply

operating current from 250µA (400µA max) to typically

40µA in shutdown mode.

5V, Low-Power, Parallel-Input,

Voltage-Output, 10-Bit DAC

10

______________________________________________________________________________________

MAX503

10-BIT DAC LATCH

NBL

INPUT

LATCH

NBH

INPUT

LATCH

NBM

INPUT

LATCH

D6/S0

D7/S1

D8/D0

D2

D9/D1

D4

D3

D5

POWER-ON

RESET

CONTROL

LOGIC

DAC

A0

A1

CS

WR

LDAC

CLR

33

µF

2.048V

REFERENCE

REFOUT

REFIN

ROFS

RFB

+5V

DGND

2N7002

REFGND

AGND

CLR

Figure 3. Low-Current Shutdown Mode

CLR CS WR LDAC

A0

A1

DATA UPDATED

L

X

X

X

X

X

Reset DAC latches

H

H

X

H

X

X

No operation

H

X

H

H

X

X

No operation

H

L

L

H

H

H

NBH (D6–D9)

H

L

L

H

H

L

NBM (D2–D5)

H

L

L

H

L

H

NBL (S0 = 0, S1 = 0,

D0, D1)

H

H

H

L

X

X

Update DAC only

H

L

L

X

L

L

NBL and NBM (S0, S1,

D0–D5), DAC not

updated

H

L

L

L

H

H

NBH and update DAC

Table 2. Input Latch Addressing