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ICS831724I 데이터시트(PDF) 8 Page - Integrated Device Technology

부품명 ICS831724I
상세설명  LVCMOS interface levels for all control inputs
PDF  24 Pages
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제조업체  IDT [Integrated Device Technology]
홈페이지  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS831724I 데이터시트(HTML) 8 Page - Integrated Device Technology

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ICS831724AKI REVISION A MAY 16, 2013
8
©2013 Integrated Device Technology, Inc
ICS831724I Data Sheet
DIFFERENTIAL CLOCK DATA MULTIPLEXER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower.
The phase noise is dependent on the input source and measurement
equipment. The source generator is the Rohde & Schwarz SMA
100A. Phase noise is measured using an Agilent E5052A Signal
Source Analyzer.
Offset from Carrier Frequency (Hz)
Additive Phase Jitter @ 100MHz
12kHz to 20MHz = 0.357ps (typical)



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