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ICS84330CI 데이터시트(PDF) 6 Page - Integrated Device Technology |
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ICS84330CI 데이터시트(HTML) 6 Page - Integrated Device Technology |
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6 / 20 page ![]() ICS84330CVI REVISION A JANUARY 7, 2011 6 ©2011 Integrated Device Technology, Inc. ICS84330CI Data Sheet 720MHZ, CRYSTAL-TO-LVPECL FREQUENCY SYNTHESIZER Table 5. Crystal Characteristics Table 6. Input Frequency Characteristics, VCC = 3V±5%, VEE = 0V, TA = -40°C to 85°C NOTE 1: For the crystal frequency range, the M value must be set to achieve the minimum or maximum VCO frequency range of 250MHz to 720MHz. Using the minimum input frequency of 10MHz, valid values of M are 200 M 511. Using the maximum input frequency of 25MHz, valid values of M are 80 M 230. NOTE 2: Maximum frequency on FREF_EXT is dependent on the internal M counter limitations. See Application Information Section for recommendations on optimizing the performance using the FREF_EXT input. AC Electrical Characteristics Table 7. AC Characteristics, VCC = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. See Parameter Measurement Information section. NOTE: Characterized using 16MHz XTAL. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: See Applications section. Parameter Test Conditions Minimum Typical Maximum Units Mode of Oscillation Fundamental Frequency 10 25 MHz Equivalent Series Resistance (ESR) 50 Shunt Capacitance 7pF Symbol Parameter Test Conditions Minimum Typical Maximum Units fIN Input Frequency XTAL; NOTE 1 10 25 MHz S_CLOCK 50 MHz FREF_EXT; NOTE 2 10 MHz Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency 720 MHz tjit(per) Period Jitter, RMS; NOTE 1. 2 6 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 1, 2 fOUT 43.75MHz 40 ps fOUT < 43.75MHz 50 ps tR / tF Output Rise/Fall Time 20% to 80% 200 600 ps tS Setup Time S_DATA to S_CLOCK 20 ns S_CLOCK to S_LOAD 20 ns M, N to nP_LOAD 20 ns tH Hold Time S_DATA to S_CLOCK 20 ns M, N to nP_LOAD 20 ns tL PLL Lock Time 10 ms odc Output Duty Cycle 45 55 % |
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