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MAX5202ACUB 데이터시트(PDF) 3 Page - Maxim Integrated Products

부품명 MAX5202ACUB
상세설명  Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in μMAX
PDF  13 Pages
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제조업체  MAXIM [Maxim Integrated Products]
홈페이지  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX5202ACUB 데이터시트(HTML) 3 Page - Maxim Integrated Products

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Low-Cost, Voltage-Output, 16-Bit DACs with
Internal Reference in µMAX
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS—MAX5200/MAX5201 (continued)
(VDD = +4.75V to +5.25V, fSCLK = 10MHz (50% duty cycle), output load = 10k
Ω in parallel with 250pF, TA = TMIN to TMAX, unless other-
wise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INTERNAL REFERENCE
VREF Output Voltage
TA = +25°C
2.48
2.5
2.52
V
TA = 0°C to +70°C
±15
VREF Tempco
TA = -40°C to +105°C
±20
ppm/°C
DIGITAL INPUTS (DIN, SCLK,
CS, CLR, LDAC)
Input High Voltage
VIH
2.4
V
Input Low Voltage
VIL
0.8
V
Input Hysteresis
VHYST
200
mV
Input Leakage
IIN
Digital inputs = 0 or VDD
±1
µA
Input Capacitance
CIN
15
pF
POWER REQUIREMENTS
Positive Power Supply
VDD
4.75
5.25
V
Positive Supply Current
IDD
All digital inputs at 0 or VDD (Note 5)
0.8
1.5
mA
Shutdown Supply Current
ISHDN
All digital inputs at 0 or VDD
110
µA
TIMING CHARACTERISTICS
SCLK Frequency
fSCLK
10
MHz
SCLK Clock Period
tCP
100
ns
SCLK Pulse Width High
tCH
40
ns
SCLK Pulse Width Low
tCL
40
ns
DIN Setup Time
tDS
40
ns
DIN Hold Time
tDH
0ns
CS Fall to SCLK Rise Setup Time
tCSS
40
ns
SCLK Rise to CS Rise Hold Time
tCSH
0ns
SCLK Rise to CS Fall Ignore
tCS0
10
ns
CS Rise to SCLK Rise Ignore
tCS1
40
ns
LDAC Pulse Width
tLDAC
40
ns
CS Rise to LDAC Low Setup
tLDACS
40
ns
SCLK Fall to CS Fall Ignore
tCSOL
10
ns
CS Pulse Width Low for Shutdown
tCSWL
40
ns
CS Pulse Width High
tCSWH
100
ns



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