ST111 datasheet(11/23 Pages) SII

11 / 23 page

HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR

Rev.3.1_00

S-T111 Series

Seiko Instruments Inc.



Operation

1. Basic operation

Figure 11 shows the block diagram of the S-T111 Series.

The error amplifier compares the reference voltage (Vref) with feedback voltage (Vfb), which is the output

voltage resistance-divided by feedback resistors (Rs and Rf). It supplies the gate voltage necessary to

maintain the constant output voltage which is not influenced by the input voltage and temperature

change, to the output transistor.

*1. Parasitic diode

VSS

Current

supply

−

Vfb

Vref

VIN

VOUT

Error

amplifier

Reference voltage

circuit

Figure 11

2. Output transistor

In the S-T111 Series, a low on-resistance P-channel MOS FET is used as the output transistor.

Be sure that VOUT does not exceed VIN

+ 0.3 V to prevent the voltage regulator from being damaged due

to reverse current flowing from the VOUT pin through a parasitic diode to the VIN pin, when the potential

of VOUT became higher than VIN.

ST111 데이터시트(PDF) 11 Page - Seiko Instruments Inc