SUPER-SMALL PACKAGE 2-CIRCUIT HIGH RIPPLE-REJECTION LOW CURRENT CONSUMPTION LOW DROPOUT CMOS VOLTAGE REGULATOR

S-1721 Series

Seiko Instruments Inc.

21

Operation

1. Basic operation

Figure 23 shows the block diagram of S-1721 Series.

not influenced by the input voltage and temperature change, to the output transistor.

*1

*1.

Parasitic diode

VSS

Current

supply

−

+

VIN

VOUT

Error

amplifier

Reference voltage

circuit

Figure

23

2. Output transistor

In the S-1721 Series, a low on-resistance P-channel MOS FET is used as the output transistor.

current flowing from the VOUT pin through a parasitic diode to the VIN pin.