| 전자부품 데이터시트 검색엔진 |
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S1003 데이터시트(PDF) 32 Page - Seiko Instruments Inc |
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S1003 데이터시트(HTML) 32 Page - Seiko Instruments Inc |
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32 / 42 page ![]() MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR S-1003 Series Rev.1.0_00 Seiko Instruments Inc. 32 12. Delay time (tD) vs. Temperature (Ta) S-1003NA12 CD = 4.7 nF, VDD = 0.95 V → −VDET(S) + 1.0 V 12 11 10 9 8 −40 85 75 50 25 0 −25 Ta [ °C] S-1003NA24 CD = 4.7 nF, VDD = 0.95 V → −VDET(S) + 1.0 V 12 11 10 9 8 −40 85 75 50 25 0 −25 Ta [ °C] S-1003NA50 CD = 4.7 nF, VDD = 0.95 V → −VDET(S) + 1.0 V 12 11 10 9 8 −40 85 75 50 25 0 −25 Ta [ °C] 1 μs tD VDD × 90% Input voltage Output voltage VIL *2 VSS VIH *1 *1. VIH = −VDET(S) + 1.0 V *2. VIL = 0.95 V V R *1 100 k Ω VDD V CD VSS VDD OUT CD + + MR *2 *1. R is unnecessary for CMOS output product. *2. Set to VDD or GND (MR pin non-active). Figure 36 Test Condition for Delay Time Figure 37 Test Circuit for Delay Time Caution The above connection diagram and constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. |
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