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UCD3138A 데이터시트(PDF) 19 Page - Texas Instruments |
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UCD3138A 데이터시트(HTML) 19 Page - Texas Instruments |
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19 / 83 page ![]() EAP0 EAN0 DAC0 EADC 4 bit dithering gives 14 bits of effective resolution 97.65625 µV/LSB effective resolution X 6 bit ADC 8 mV/LSB Signed 9 bit result (error) 1 mV /LSB AFE_GAIN 10 bit DAC 1.5625 mV/LSB Value Dither S CPCC Filter x Ramp SAR/Prebias Absolute Value Calculation Averaging 10 bit result 1.5625 mV/LSB 2 3-AFE_GAIN Peak Current Mode Comparator Peak Current Detected A0 2 AFE_GAIN IOFFSET REA EAP EAN AGND AGND IOFFSET REA Front End Differential Amplifier UCD3138A www.ti.com SLUSC66B – MARCH 2015 – REVISED MAY 2015 Figure 5-5. Input Stage of EADC Module Figure 5-6. Front End Module (Front End 2 Recommended for Peak Current Mode Control) 5.8.1.2 DPWM Module The DPWM module represents one complete DPWM channel with 2 independent outputs, A and B. Multiple DPWM modules within the UCD3138A system can be configured to support all key power topologies. DPWM modules can be used as independent DPWM outputs, each controlling one power supply output voltage rail. It can also be used as a synchronized DPWM—with user selectable phase shift between the DPWM channels to control power supply outputs with multiphase or interleaved DPWM configurations. Copyright © 2015, Texas Instruments Incorporated Specifications 19 Submit Documentation Feedback Product Folder Links: UCD3138A |
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