MAX7652ECB datasheet(21/36 Pages) MAXIM

21 / 36 page

Since the acquisition time is limited to eight clock peri-

ods, the acquired voltage at CHOLD can have signifi-

cant error if the analog input source impedance (Rs) is

large. Limit the worst-case error to 1/2 LSB by ensuring,

Rs < 0.9 tCLK / CHOLD

where tCLK is the clock period. Smaller Rs values may

be necessary if an antialiasing filter is used.

The ADC continuously samples the positive and negative

difference between the two external reference voltages

REF+ and REF- by reconfiguring capacitor CREF over

alternate eight clock-period intervals. Switch pairs 1 and

2 are forced off and on, respectively, on the rising edge

of clock cycle five to ensure synchronization with conver-

sions. Capacitor CHOLD also charges to the difference

between REF+ and REF- on the rising edge of clock

cycle 29 and remains charged until the next conversion.

Nevertheless, continuous CREF charging requirements

dominate loading at the REF+ and REF- inputs.

Analog Inputs

The MAX7651/MAX7652 operate in either single-ended

or differential mode. In single-ended mode, one of eight

input channels (AIN0–AIN7) is assigned to AIN+, and

ACOM is assigned to AIN- (see Figure 6). In differential

mode, the eight input channels are assigned to AIN+

and AIN- with four distinct pairings. Table 6 shows the

input assignments for different values of bits M3, M2,

M1, and M0 in the A/D Control SFR (see ADC Special

Function Registers).

Analog Input Protection

Internal protection diodes clamp the analog inputs to

AVDD and AGND, so channels can swing within AGND -

Flash Programmable 12-Bit Integrated

Data-Acquisition Systems

______________________________________________________________________________________

SFR

WRITE

CLK

INPUT SAMPLE

2.1pF

VREF+

VREF-

AIN-

AIN+

1.50pF

VREF-

CREF

CHOLD

Figure 6. ADC Input Structure and Switch Timing

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