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MX019 데이터시트(PDF) 5 Page - CML Microcircuits |
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MX019 데이터시트(HTML) 5 Page - CML Microcircuits |
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5 / 13 page ![]() Quad Digital Control Amplifier 5 MX019 1998 MX-COM, INC. www.mxcom.com Tel: 800 638 5577 910 744 5050 Fax: 910 744 5054 Doc. # 20480077.006 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies 3. External Components V DD V DD C 6 C 1 C 2 C 3 C 4 C 5 V SS V BIAS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SERIAL CLOCK INPUT CONTROL DATA INPUT CHIP ADDRESS CHANNEL 1 OUTPUT CHANNEL 2 OUTPUT CHANNEL 3 OUTPUT CHANNEL 4 OUTPUT CHANNEL 1 INPUT CHANNEL 2 INPUT CHANNEL 3 INPUT CHANNEL 4 INPUT LOAD/LATCH LOAD/LATCH MX019J C1 to C4 0.1µF ± 20% C5 1.0µF ± 20% C6 1.0µF ± 20% Figure 2: Recommended External Components Notes: 1. Channel Amplifiers 1 to 4 are inverting amplifiers. 2. Analog input capacitors C1 to C4 are only required for AC input signals, DC input signals do not require these components. 4. General Description 4.1 Control Data and Timing The gain of each amplifier block (Channel 1 to Channel 4) in the MX019 is set by a separate 8-bit data word (bit 7 to bit 0). This 8-bit word, consisting of 4 Address bits (bit 7 to bit 4) and 4 Gain Control bits (bit 3 to bit 0), is loaded to the Control Data Input in serial format using the external data clock. 4.1.1 Data Loading The 8-bit data word is loaded bit 7 first and bit 0 last. Bit 7 must be a logic “1” to address the chip. If bit 7 in the word is a logic “0” that 8-bit word will not be executed. The Chip Address input permits the use of two devices in a system by indicating to the chip what its address is, a “1” or a “0.” Bit 6 in the address section of the control word is then used to select which device is being controlled. Figure 3 shows the timing information required to load and operate this device. Data is loaded to the MX019 on the rising edge of the Serial Clock. Loaded data is executed on the falling (rising) edge of the Load/ Latch ( Load /Latch) pulse. Table 1 shows the format of each 4-bit Address word, Table 2 shows the format of each Gain Control word with Figure 3 describing the data loading operation and timing. |
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