UC5301

CMOS IC

UNISONICTECHNOLOGIESCO.,LTD

5 of 8

www.unisonic.com.tw

QW-R502-602.C



APPLICATION INFORMATION

Table 1. Low-ESR Capacitor Manufacturers

PRODUCTION METHOD

MANUFACTURER

SERIES

Surface-Mount Ceramic

AVX

X7R

Matsuo

X7R

Capacitor Selection

Proper selection of external capacitor in applications is critical to keep the lowest output resistance; the capacitors

should be with low ESR (Table 1). Minimizing the charge-pump capacitor’s ESR minimizes the total output

resistance because the charge-pump output resistance is a function of C1’s and C2’s ESR.

Flying Capacitor (C1)

Increasing the flying capacitor’s value reduces the output resistance. Above a certain point, increasing C1’s

capacitance has a negligible effect because the output resistance becomes dominated by the internal switch

resistance and capacitor ESR.

Output Capacitor (C2)

Increasing the output capacitor’s value reduces the output ripple voltage. Decreasing its ESR reduces both output

resistance and ripple. Lower capacitance values can be used with light loads if higher output ripple can be tolerated.

The peak-to-peak ripple is determined by the following equations:

C2

L

OSC

L

ESR

2XI

C2

f

I







The output voltage drop is the load current times the output resistance, and the power efficiency is calculated as:

η=

)

(V

I

R

I

R

I

R

I

P

P

IN

Q

OUT

2

L

L

2

L

L

2

L

N

I

OUT







Input Bypass Capacitor (C3)

Input bypass capacitor is used to bypass the incoming supply to reduce its AC impedance and the impact of the

UTC UC5301’s switching noise. The value of a bypass capacitor is recommended to be equal to the C1.

Voltage Inverter

The device is mainly for application as a charge-pump voltage inverter (Figure 2). Less external capacitors are

required. (C1, C2 and a bypass capacitor, if necessary.)

Layout and Grounding

For a better noise performance, a good layout is necessary. Therefore, it’s best to mount all components as close

together as possible, keep traces short to minimize parasitic inductance and capacitance and use a ground plane.