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M4334G-S08-R 데이터시트(PDF) 5 Page - Unisonic Technologies

부품명 M4334G-S08-R
상세설명  STEREO AUDIO D/A CONVERTER 24BITS,96KHZ SAMPLING
PDF  9 Pages
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제조업체  UTC [Unisonic Technologies]
홈페이지  http://www.utc-ic.com
Logo UTC - Unisonic Technologies

M4334G-S08-R 데이터시트(HTML) 5 Page - Unisonic Technologies

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M4334
CMOS IC
UNISONICTECHNOLOGIESCO.,LTD
5 of 9
www.unisonic.com.tw
QW-R502-441A
ELECTRICAL CHARACTERISTICS (Cont.)
Base-Rate Mode
High-Rate Mode
PARAMETER
SYMBOL
TEST
CONDITIONS MIN
TYP
MAX
MIN
TYP
MAX
UNIT
Ambient Operating Temperature
TOPR
-40
85
-40
85
°C
16-bit ,
un-weighted
83
91
88
16-bit ,
a-weighted
86
94
86
94
18 to 24-bit,
un-weighted
85
93
90
Dynamic Range
18 to 24-bit ,
a-weighted
88
96
88
96
dB
16-bit,
0dB
-86
-70
-86
-80
16-bit,
-20dB
-71
-63
-68
-60
16-bit,
-60dB
-31
-23
-28
-20
18 to 24-bit,
0dB
-88
-82
-88
-82
18 to 24-bit,
-20dB
-73
-65
-70
-62
Total Harmonic Distortion
+Noise
THD+N
18 to 24-bit,
-60dB
-33
-25
-30
-22
dB
SWITCHING CHARCTERISTICS
(TA=-40 to 85°C;VA=4.75V~5.5V; Input: Logic 0=0V, Logic 1=VA, CL=20pF)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP MAX UNIT
Input Sample Rate
fS
2
100
kHz
MCLK Pulse Width High
MCLK/LRCK=512
10
1000
ns
MCLK Pulse Width Low
MCLK/LRCK=512
10
1000
ns
MCLK Pulse Width High
MCLK/LRCK=384 or 192
21
1000
ns
MCLK Pulse Width Low
MCLK/LRCK=384 or 192
21
1000
ns
MCLK Pulse Width High
MCLK/LRCK=256 or 128
31
1000
ns
MCLK Pulse Width Low
MCLK/LRCK=256 or 128
31
1000
ns
EXTERNAL SCLK MODE
LRCK Duty Cycle
40
50
60
%
SCLK Pulse Width High
tSCLKH
20
ns
SCLK Pulse Width Low
tSCLKL
20
ns
MCLK/LRCK=512,256 or 384
1
(128) Fs
ns
SCLK Period
tSCLKW
MCLK/LRCK=128 or 192
1
(64) Fs
ns
SCLK rising to LRCK edge delay
tSLRD
20
ns
SCLK rising to LRCK edge setup time
tSLRS
20
ns
SDATA valid to SCLK rising setup time
tSDLRS
20
ns
SCLK rising to SDATA hold time
tSDH
20
ns
INTERNAL SCLK MODE
LRCK duty cycle
50
%
SCLK Period
tSCLKW
1
SCLK
ns
SCLK rising to LRCK edge
tSCLKR
tsclkw
2
μs
SDATA valid to SCLK rising setup time
tSDLRS
1
10
(512) Fs
+
ns
SCLK rising to SDATA hold time
tSDH
MCLK/LRCK=128 , 256 or 512
1
+15
(512) Fs
ns
SCLK rising to SDATA hold time
tSDH
MCLK/LRCK=192 or 384
1
15
(384) Fs
+
ns



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