 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
LMH6502MT/NOPB 데이터시트(PDF) 4 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
LMH6502MT/NOPB 데이터시트(HTML) 4 Page - Texas Instruments |
|
|
4 / 29 page  LMH6502 SNOSA65D – OCTOBER 2003 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (1) (continued) Unless otherwise specified, all limits specified for TJ = 25°C, VS = ±5V, AV(MAX) = 10, VCM = 0V, RF = 1kΩ, RG = 174Ω, VIN_DIFF = ±0.1V, RL = 100Ω, VG = +2V. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min(2) Typ(2) Max(2) Units DP Differential Phase f = 4.43MHz, RL = 150Ω, Neg. 0.10 deg Sync DC & Miscellaneous Performance GACCU Gain Accuracy (See Application VG = 2.0V 0.0 +0.6 dB Information) 1V < VG < 2V +0.6/ −0.3 +3.1/ −3.6 G Match Gain Matching (See Application VG = 2.0V – ±0.6 dB Information) 1 < VG < 2V – +2.8/ −3.9 K Gain Multiplier (See Application 1.61 1.72 1.84 V/V Information) 1.58 1.91 VCM Input Voltage Range Pin 3 & 6 Common Mode, ±2.0 ±2.2 V |CMRR| > 55dB(5) ±1.70 VIN_DIFF Differential Input Voltage Between pins 3 & 6 ±0.3 ±0.39 V ±0.12 I RG_MAX RG Current Pins 4 & 5 ±1.70 ±2.22 mA ±1.56 IBIAS Bias Current Pins 3 & 6(6) 9 18 20 µA Pins 3 & 6(6), 2.5 5 VS = ±2.5V 6 TC IBIAS Bias Current Drift Pin 3 & 6(7) 100 nA/°C I OFF Offset Current Pin 3 & 6 0.01 2.0 µA 3.6 TC IOFF Offset Current Drift See(7) 5 nA/°C RIN Input Resistance Pin 3 & 6 750 k Ω CIN Input Capacitance Pin 3 & 6 5 pF IVG VG Bias Current Pin 2, VG = 0V (6) −300 µA TC IVG VG Bias Drift Pin 2(7) 20 nA/°C R VG VG Input Resistance Pin 2 10 k Ω C VG VG Input Capacitance Pin 2 1.3 pF VOUT Output Voltage Range RL = 100Ω ±3.00 ±3.20 ±2.95 V RL = Open ±3.95 ±4.00 ±3.82 ROUT Output Impedance DC 0.1 Ω IOUT Output Current VOUT = ±4V from Rails ±80 ±90 mA ±75 VO OFFSET Output Offset Voltage 0V < VG < 2V ±80 ±300 mV ±380 +PSRR +Power Supply Rejection Ratio(8) Input Referred, 1V change, −69 −47 dB VG = 2.2V −45 −PSRR −Power Supply Rejection Ratio(8) Input Referred, 1V change, −58 −41 dB VG = 2.2V −40 CMRR Common Mode Rejection Ratio(5) Input Referred,VG = 2V −72 dB −1.8V < VCM < 1.8V IS Supply Current No Load 27 38 41 mA VS = ±2.5V, RL= Open 9.3 16 19 (5) CMRR definition: [| ΔVOUT/ΔVCM| / AV] with 0.1V differential input voltage. (6) Positive current corresponds to current flowing in the device. (7) Drift determined by dividing the change in parameter distribution average at temperature extremes by the total temperature change. (8) +PSRR definition: [| ΔVOUT/ΔV +| / A V], −PSRR definition: [|ΔVOUT/ΔV −| / A V] with 0.1V differential input voltage. 4 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMH6502 |
|
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
