PUSB3AB6

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© NXP Semiconductors N.V. 2015. All rights reserved.

Product data sheet

Rev. 1 — 3 March 2015

6 of 12

NXP Semiconductors

PUSB3AB6

ESD protection for ultra high-speed interfaces

The device uses an advanced clamping structure showing a negative dynamic resistance.

This snapback behavior strongly reduces the clamping voltage to the system behind the

ESD protection during an ESD event. Do not connect unlimited DC current sources to the

data lines to avoid keeping the ESD protection device in snapback state after exceeding

breakdown voltage (due to an ESD pulse for instance).

Fig 6.

Dynamic resistance with positive clamping;

typical values

Fig 7.

Dynamic resistance with negative clamping;

typical values

Fig 8.

Dynamic resistance with positive clamping;

typical values

Fig 9.

Dynamic resistance with negative clamping;

typical values

025

20

10

15

5

aaa-016902

10

15

5

20

25

(A)

0

-25

0

-5

-15

-10

-20

aaa-016903

-15

-10

-20

-5

0

(A)

-25

025

20

10

15

5

aaa-016904

10

15

5

20

25

(A)

0

-25

0

-5

-15

-10

-20

aaa-016905

-15

-10

-20

-5

0

(A)

-25