UTDA8024 datasheet(3/15 Pages) UTC

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UTDA8024

Preliminary

LINEAR INTEGRATED CIRCUIT

UNISONICTECHNOLOGIESCO.,LTD

3 of 15

www.unisonic.com.tw

QW-R113-014.a



PIN DESCRIPTION

PIN NO.

PIN NAME

DESCRIPTION

CLKDIV1

CLK frequency selection input 1

CLKDIV2

CLK frequency selection input 2

5V/ V

Card supply voltage selection input; VCC=5V (HIGH) or VCC=3V (LOW)

PGND

DC/DC converter power supply ground

DC/DC converter capacitor; connected between pins S1 and S2; C=100nF with

ESR<100mΩ

VDDP

DC/DC converter power supply voltage

DC/DC converter capacitor; connected between pins S1 and S2; C=100nF with

ESR<100mΩ

VUP

DC/DC converter output decoupling capacitor connection; C=100nF with ESR<100mW

must be connected between VUP and PGND

PRES

Card presence contact input (active LOW); if PRES or PRES is active, the card is

considered ‘present’ and a built-in debounce feature of 8 ms (typ.) is activated

PRES

Card presence contact input (active HIGH); if PRES or PRES is active, the card is

considered ‘present’ and a built-in debounce feature of 8 ms (typ.) is activated

I/O

Data line to/from card reader contact C7; integrated 11kΩ pull-up resistor to VCC

AUX2

Data line to/from card reader contact C8; integrated 11kΩ pull-up resistor to VCC

AUX1

Data line to/from card reader contact C4; integrated 11kΩ pull-up resistor to VCC

CGND

Card signal ground

CLK

Card clock to/from card reader contact C3

RST

Card reset output from card reader contact C2

VCC

Card supply voltage to card reader contact C1; decoupled to CGND via 2 × 100nF or

100+220nF capacitors with ESR<100mΩ; Note 1

PORADJ

Power-on reset threshold adjustment input for changing the reset threshold with an

external resistor bridge; doubles the width of the POR pulse when used

CMDVCC

Input from the host to start activation sequence (active LOW)

RSTIN

Card reset input from the host

VDD

Supply voltage

GND

Ground

OFF

NMOS interrupt output to the host (active LOW); 20kΩ integrated pull-up resistor to VDD

XTAL1

Crystal connection or input for external clock

XTAL2

Crystal connection (leave open-circuit if external clock source is used)

I/OUC

Host data I/O line; integrated 11kΩ pull-up resistor to VDD

AUX1UC

Auxiliary data line to/from the host; integrated 11kΩ pull-up resistor to VDD

AUX2UC

Auxiliary data line to/from the host; integrated 11 kΩ pull-up resistor to VDD

Note 1. The noise margin on VCC will be higher with the 220nF capacitor

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