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TPL0102-100QPWREP 데이터시트(PDF) 14 Page - Texas Instruments

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부품명 TPL0102-100QPWREP
상세설명  TPL0102-EP 256-Taps Dual-Channel Digital Potentiometer With Non-Volatile Memory
PDF  36 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI - Texas Instruments

TPL0102-100QPWREP 데이터시트(HTML) 14 Page - Texas Instruments

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Start
Address (1010 000b)
0
Ack
IVRA Register (0x00h)
Ack
Method 1: First Write 0x80 to IVRA and then write 0x80 to IVRB Register
From Processor to DPOT
From DPOT to Processor
Data (0x80)
Ack
Stop
Start
Address (1010 000b)
0
Ack
IVRB Register (0x01h)
Ack
Data (0x80h)
Ack
Stop
Start
Address (1010 000b)
0
Ack
IVRA Register (0x00h)
Ack
Data (0x80h)
Ack
Stop
Method 2: Perform a multi byte write to IVRA and IVRB Register
Ack
Data (0x80h)
Data written to Register 0x01 h
Data written to Register 0x00h
TPL0102-EP
SLIS149 – JUNE 2014
www.ti.com
The following is a sample sequence to set wipers of both potentiometers at mid-scale. Assume A0, A1, and A2
are 0 and device has just been powered up.
Figure 14. tI2C Interface Example
8.3.2 Standard I2C Interface Details
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by the master sending a start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 15). After the start condition, the device address
byte is sent, MSB first, including the data direction bit (R/W). This device does not respond to the general call
address. After receiving the valid address byte, this device responds with an ACK, a low on the SDA input/output
during the high of the ACK-related clock pulse
Figure 15. Definition of Start and Stop Conditions
14
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Copyright © 2014, Texas Instruments Incorporated



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