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SY100S321JC 데이터시트(PDF) 1 Page - Micrel Semiconductor |
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SY100S321JC 데이터시트(HTML) 1 Page - Micrel Semiconductor |
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1 / 5 page ![]() 18 17 16 15 14 13 1 2 3 4 5 6 7 24 8 23 9 22 10 21 11 20 12 19 Top View Flatpack F24-1 D1 D3 D2 VCCA O3 O2 D5 D4 VCCA Q6 Q5 Q4 D1 O2 D2 D3 O4 D4 D5 O6 D6 D7 O8 D8 D9 O1 O3 O5 O7 O9 4 3 2 1 28 27 12 13 14 15 16 17 19 11 20 10 21 9 22 8 23 7 24 6 Top View PLCC J28-1 D6 VEE VCCA D7 D8 VEES D9 26 18 25 5 VCCA VCC VCC O9 O7 O8 O1 LOW-POWER 9-BIT INVERTER s Max. propagation delay of 700ps s IEE min. of –55mA s Extended supply voltage option: VEE = –4.2V to –5.5V s Voltage and temperature compensation for improved noise immunity s 70% faster than Fairchild 300K at lower power s Internal 75K Ω input pull-down resistors s Function and pinout compatible with Fairchild F100K s Available in 24-pin CERPACK and 28-pin PLCC packages FEATURES PIN CONFIGURATIONS BLOCK DIAGRAM The SY100S321 is a monolithic 9-bit inverter. The device contains nine inverting buffer gates with single input and output. DESCRIPTION SY100S321 Rev.: G Amendment: /0 Issue Date: July, 1999 Pin Function D1 – D9 Data Inputs Q1 – Q9 Data Outputs VEES VEE Substrate VCCA VCCO for ECL Outputs PIN NAMES 1 |
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