24LC64-EP datasheet(4/12 Pages) MICROCHIP

4 / 12 page

24AA64/24LC64/24FC64

DS21189L-page 4

FIGURE 1-1:

BUS TIMING DATA

TAA

Output valid from clock

(Note 2)

—

3500

900

400

1.7V

≤ VCC < 2.5V

2.5V

≤ VCC ≤ 5.5V

1.7V

≤ VCC < 2.5V 24FC64

2.5V

≤ VCC ≤ 5.5V 24FC64

TBUF

Bus free time: Time the bus

must be free before a new

transmission can start

4700

1300

500

—

1.7V

≤ VCC < 2.5V

2.5V

≤ VCC ≤ 5.5V

1.7V

≤ VCC < 2.5V 24FC64

2.5V

≤ VCC ≤ 5.5V 24FC64

TOF

Output fall time from VIH

minimum to VIL maximum

≤ 100 pF

10 + 0.1CB

250

All except, 24FC64 (Note 1)

24FC64 (Note 1)

TSP

Input filter spike suppression

(SDA and SCL pins)

—

All except, 24FC64 (Notes 1

and 3)

TWC

Write cycle time (byte or

page)

—5

—

Endurance

1,000,000

—

cycles

25°C (Note 4)

AC CHARACTERISTICS

Electrical Characteristics:

Industrial (I):

VCC = +1.7V to 5.5V

TA = -40°C to +85°C

Automotive (E):

VCC = +2.5V to 5.5V

TA = -40°C to 125°C

Param.

No.

Sym.

Characteristic

Min.

Max.

Units

Conditions

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved

noise spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site

at www.microchip.com.

(unprotected)

(protected)

SCL

SDA

OUT

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