25AA640/25LC640/25C640

DS21223A-page 10

Preliminary

© 1997 Microchip Technology Inc.

3.7

Data Protection

The following protection has been implemented to pre-

vent inadvertent writes to the array:

• The write enable latch is reset on power-up.

• A write enable instruction must be issued to set

the write enable latch.

• After a byte write, page write, or status register

write, the write enable latch is reset.

• CS must be set high after the proper number of

clock cycles to start an internal write cycle.

• Access to the array during an internal write cycle

is ignored and programming is continued.

3.8

Power On State

The 25xx640 powers on in the following state:

• The device is in low power standby mode (CS = 1).

• The write enable latch is reset.

• SO is in high impedance state.

• A high to low transition on CS is required to enter

the active state.

.

TABLE 3-3:

WRITE PROTECT FUNCTIONALITY MATRIX

WPEN

WP

WEL

Protected Blocks

Unprotected Blocks

Status Register

X

X

0

Protected

Protected

Protected

0

X

1

Protected

Writable

Writable

1

Low

1

Protected

Writable

Protected

X

High

1

Protected

Writable

Writable