PIC16C925-SSLASHCL datasheet(55/182 Pages) MICROCHIP

55 / 182 page

 2001 Microchip Technology Inc.

Preliminary

DS39544A-page 53

PIC16C925/926

8.0

CAPTURE/COMPARE/PWM

(CCP) MODULE

The CCP (Capture/Compare/PWM) module contains a

16-bit register which can operate as a 16-bit capture

master/slave duty cycle register. Table 8-1 shows the

timer resources used by the CCP module.

The Capture/Compare/PWM Register1 (CCPR1) is

comprised of two 8-bit registers: CCPR1L (low byte)

and CCPR1H (high byte). The CCP1CON register con-

trols the operation of CCP1. All three are readable and

writable.

For use of the CCP module, refer to the Embedded

Control Handbook, “Using the CCP Modules” (AN594).

TABLE 8-1:

CCP MODE - TIMER

RESOURCE

CCP1CON REGISTER (ADDRESS 17h)

CCP Mode

Timer Resource

Capture

Compare

PWM

Timer1

Timer2

U-0

R/W-0

—

CCP1X

CCP1Y

CCP1M3

CCP1M2

CCP1M1

CCP1M0

bit 7

bit 0

bit 7-6

Unimplemented: Read as '0'

bit 5-4

CCP1X:CCP1Y: PWM Least Significant bits

Capture mode:

Unused

Compare mode:

Unused

PWM mode:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.

bit 3-0

CCP1M3:CCP1M0: CCP1 Mode Select bits

0000

= Capture/Compare/PWM disabled (resets CCP1 module)

0100

= Capture mode, every falling edge

0101

= Capture mode, every rising edge

0110

= Capture mode, every 4th rising edge

0111

= Capture mode, every 16th rising edge

1000

= Compare mode, set output on match (bit CCP1IF is set)

1001

= Compare mode, clear output on match (bit CCP1IF is set)

1010

= Compare mode, generate software interrupt-on-match (bit CCP1IF is set, CCP1 pin is

unaffected)

1011

= Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1)

11xx

= PWM mode

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

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