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PIC16C925-S/CL 데이터시트(PDF) 158 Page - Microchip Technology

부품명 PIC16C925-S/CL
상세설명  64/68-Pin CMOS Microcontrollers with LCD Driver
PDF  182 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC16C925-S/CL 데이터시트(HTML) 158 Page - Microchip Technology

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PIC16C925/926
DS39544A-page 156
Preliminary
 2001 Microchip Technology Inc.
FIGURE 15-15:
I2C BUS DATA TIMING
TABLE 15-10: I2C BUS DATA REQUIREMENTS
90
91
92
100
101
103
106
107
109
109
110
102
SCL
SDA
In
SDA
Out
Note:
Refer to Figure 15-4 for load conditions.
Parameter
No.
Symbol
Characteristic
Min
Max
Units
Conditions
100
THIGH
Clock high time
100 kHz mode
4.0
—
µs
Device must operate at a
minimum of 1.5 MHz
SSP Module
1.5TCY
—
101
TLOW
Clock low time
100 kHz mode
4.7
—
µs
Device must operate at a
minimum of 1.5 MHz
SSP Module
1.5TCY
—
102
TR
SDA and SCL rise
time
100 kHz mode
—
1000
ns
103
TF
SDA and SCL fall
time
100 kHz mode
—
300
ns
90
TSU:STA
START condition
setup time
100 kHz mode
4.7
—
µs
Only relevant for Repeated
START condition
91
THD:STA
START condition
hold time
100 kHz mode
4.0
—
µs
After this period the first
clock pulse is generated
106
THD:DAT
Data input hold
time
100 kHz mode
0
—
ns
107
TSU:DAT
Data input setup
time
100 kHz mode
250
—
ns
92
TSU:STO
STOP condition
setup time
100 kHz mode
4.7
—
µs
109
TAA
Output valid from
clock
100 kHz mode
—
3500
ns
(Note 1)
110
TBUF
Bus free time
100 kHz mode
4.7
—
µs
Time the bus must be free
before a new transmission
can start
D102
CB
Bus capacitive loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.



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