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PIC16C72-04/SS 데이터시트(PDF) 15 Page - Microchip Technology |
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PIC16C72-04/SS 데이터시트(HTML) 15 Page - Microchip Technology |
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15 / 124 page ![]() PIC16C72 Series © 1998 Microchip Technology Inc. Preliminary DS39016A-page 15 2.3 PCL and PCLATH The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 13 bits wide. The low byte is called the PCL register. This reg- ister is readable and writable. The high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly readable or writable. All updates to the PCH register go through the PCLATH register. Figure 2-9 shows the four situations for the loading of the PC. Example 1 shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH). Example 2 shows how the PC is loaded during a GOTO instruction (PCLATH<4:3> → PCH). Example 3 shows how the PC is loaded during a CALL instruction (PCLATH<4:3> → PCH), with the PC loaded (PUSHed) onto the Top of Stack. Finally, example 4 shows how the PC is loaded during one of the return instructions where the PC is loaded (POPed) from the Top of Stack. FIGURE 2-9: LOADING OF PC IN DIFFERENT SITUATIONS PC 12 8 7 0 5 PCLATH<4:0> PCLATH ALU result Opcode <10:0> 8 PC 12 11 10 0 11 PCLATH<4:3> PCH PCL 8 7 2 PCLATH PCH PCL Situation 1 - Instruction with PCL as destination Situation 2 - GOTO Instruction STACK (13-bits x 8) Top of STACK STACK (13-bits x 8) Top of STACK Opcode <10:0> PC 12 11 10 0 11 PCLATH<4:3> 8 7 2 PCLATH PCH PCL Situation 3 - CALL Instruction STACK (13-bits x 8) Top of STACK Opcode <10:0> PC 12 11 10 0 11 8 7 PCLATH PCH PCL Situation 4 - RETURN, RETFIE, or RETLW Instruction STACK (13-bits x 8) Top of STACK 13 13 Note: PCLATH is not updated with the contents of PCH. |
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