PIC16C72-10SLASHSS datasheet(33/288 Pages) MICROCHIP

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DS30390E-page 33

PIC16C7X

4.2.2.4

PIE1 REGISTER

This register contains the individual enable bits for the

peripheral interrupts.

Applicable Devices

72 73 73A 74 74A 76 77

Note:

Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

FIGURE 4-10: PIE1 REGISTER PIC16C72 (ADDRESS 8Ch)

U-0

R/W-0

U-0

R/W-0

—

ADIE

—

SSPIE

CCP1IE

TMR2IE

TMR1IE

= Readable bit

W = Writable bit

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7

bit0

bit 7:

Unimplemented: Read as '0'

bit 6:

ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt

0 = Disables the A/D interrupt

bit 5-4: Unimplemented: Read as '0'

bit 3:

SSPIE: Synchronous Serial Port Interrupt Enable bit

1 = Enables the SSP interrupt

0 = Disables the SSP interrupt

bit 2:

CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

bit 1:

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt

bit 0:

TMR1IE: TMR1 Overﬂow Interrupt Enable bit

1 = Enables the TMR1 overﬂow interrupt

0 = Disables the TMR1 overﬂow interrupt

PIC16C72-10/SS 데이터시트(PDF) 33 Page - Microchip Technology

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