LP2952-N, LP2952A, LP2953, LP2953A

SNVS095F – MAY 2004 – REVISED MARCH 2015

www.ti.com

Typical Applications (continued)

8.2.1.1 Design Requirements

For this design example, use the parameters listed in Table 1 as the input parameters.

Table 1. Design Parameters

DESIGN PARAMETER

DESIGN REQUIREMENT

Input voltage

6 V, ±10%, provided by the DC-DC converter switching at 1 MHz

Output voltage

5 V, ±1%

Output current

250 mA (maximum), 1 mA (minimum)

RMS noise, 10 Hz to 100 kHz

1 mV typical

PSRR at 1 kHz

50 dB typical

8.2.1.2 Detailed Design Procedure

At 150-mA loading, the dropout of the LP2952 and LP2953 has 600-mV maximum dropout over temperature —

thus, a 1500-mV headroom is sufficient for operation over both input and output voltage accuracy. The efficiency

accordance with the External Capacitors section. Ceramic capacitances of 1

μF for the input and one 2.2-μF

capacitor for the output are selected. With an efficiency of 83.3% and a 250-mA maximum load, the internal

power dissipation is 250 mW, which corresponds to a 19.2°C junction temperature rise for the SOIC package.

of the SOIC package will rise 19.2°C above the ambient temperature. With an 85°C maximum ambient

temperature, the junction temperature is at 104.2°C. To minimize noise, a bypass capacitor of 100 pF is selected

between OUT and FEEDBACK pins.

8.2.1.3 Application Curves

Figure 34. Line Transient Response

Figure 35. Load Transient Response

22

Submit Documentation Feedback

Copyright © 2004–2015, Texas Instruments Incorporated

Product Folder Links: LP2952-N LP2952A LP2953 LP2953A