RF64 datasheet(18/76 Pages) ETC2

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ADVANCED COMMUNICATIONS & SENSING

Page 18 of 76

RF64

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LO1 Tx

Amplification

Seco

up-conv

onversion

In erpolation

DACs

DDS

filters

Waveform

LO2 Tx

generator

LO2 Tx

3.3. Transmitter Description

The RF64 is set to transmit mode when MCParam_Chip_mode = 100.

ersion

First up-c

Data

Clock

RFIO

Baseband

Figure 8: Transmitter Architecture

3.3.1. Architecture Description

The baseband I and Q signals are digitally generated by a DDS whose digital to analog converters (DAC) followed

by two anti-aliasing low-pass filters transform the digital signal into analog in-phase (I) and quadrature (Q)

components whose frequency is the selected frequency deviation (Fdev).

Fdev

I(t)

Q(t)

Figure 9: I(t), Q(t) Overview

In FSK mode, the relative phase of I and Q is switched by the input data between -90°and +90°with continuous

phase. The modulation is therefore performed at this initial stage, since the information contained in the phase

difference will be converted into a frequency shift when the I and Q signals are up-converted in the first mixer

stage. This first up-conversion stage is duplicated to enhance image rejection. The FSK convention is such that:

DATA ''1' ' Frf

DATA ''0' ' Frf

 Fdev

 Fdev

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