RF69 datasheet(46/81 Pages) ETC2

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RF69

Page 45

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The frame ends when NSS goes high. The next frame must start with an address byte. The SINGLE access mode is

actually a special case of FIFO / BURST mode with only 1 data byte transferred.

During the write access, the byte transferred from the slave to the master on the MISO line is the value of the written

5.2.2. FIFO

5.2.2.1. Overview and Shift Register (SR)

In packet mode of operation, both data to be transmitted and that has been received are stored in a configurable FIFO

(First In First Out) device. It is accessed via the SPI interface and provides several interrupts for transfer management.

The FIFO is 1 byte wide hence it only performs byte (parallel) operations, whereas the demodulator functions serially. A

shift register is therefore employed to interface the two devices. In transmit mode it takes bytes from the FIFO and outputs

them serially (MSB first) at the programmed bit rate to the modulator. Similarly, in Rx the shift register gets bit by bit data

from the demodulator and writes them byte by byte to the FIFO. This is illustrated in figure below.

byte1

byte0

FIFO

Data Tx/Rx

SR (8bits)

MSB

LSB

Figure 26. FIFO and Shift Register (SR)

Note

When switching to Sleep mode, the FIFO can only be used once the ModeReady flag is set (quasi immediate from

all modes except from Tx)

5.2.2.2. Size

The FIFO size is fixed to 66 bytes.

5.2.2.3. Interrupt Sources and Flags

 FifoNotEmpty: FifoNotEmpty interrupt source is low when byte 0, i.e. whole FIFO, is empty. Otherwise it is high.

Note that when retrieving data from the FIFO, FifoNotEmpty is updated on NSS falling edge, i.e. when FifoNotEmpty

is updated to low state the currently started read operation must be completed. In other words, FifoNotEmpty state

must be checked after each read operation for a decision on the next one (FifoNotEmpty = 1: more byte(s) to read;

FifoNotEmpty = 0: no more byte to read).

 FifoFull: FifoFull interrupt source is high when the last FIFO byte, i.e. the whole FIFO, is full. Otherwise it is low.

 FifoOverrunFlag: FifoOverrunFlag is set when a new byte is written by the user (in Tx or Standby modes) or the SR

(inRx mode) while the FIFO is already full. Data is lost and the flag should be cleared by writing a 1, note that the

FIFO will also be cleared.

 PacketSent: PacketSent interrupt source goes high when the SR's last bit has been sent.

 FifoLevel: Threshold can be programmed by FifoThreshold in RegFifoThresh. Its behavior is illustrated in figure

below.

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