TC826 datasheet(8/18 Pages) MICROCHIP

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TC826

DS21477B-page 8

4.0

THEORY OF OPERATION

4.1

Analog Section

In addition to the basic signal integrate and de-

integrate cycles discussed above, the TC826 incorpo-

rates an auto-zero cycle.This cycle removes buffer

amplifier, integrator, and comparator offset voltage

error terms from the conversion. A true digital zero

reading results without external adjusting potentiome-

ters. A complete conversion consists of three cycles:

an auto-zero, signal integrate and reference cycle

(Figure 4-1 and Figure 4-2).

4.1.1

AUTO-ZERO CYCLE

During the auto-zero cycle, the differential input signal

is disconnected from the circuit by opening internal

analog gates. The internal nodes are shorted to analog

common (internal analog ground) to establish a zero

input condition. Additional analog gates close a feed-

back loop around the offset voltage error compensation.

The voltage level established on CAZ compensates for

device offset voltages.

The auto-zero cycle length is 19 counts minimum.

Unused time in the de-integrate cycle is added to the

auto-zero cycle.

4.1.2

SIGNAL INTEGRATION CYCLE

The auto-zero loop is opened and the internal differen-

tial inputs connect to +IN and -IN. The differential input

signal is integrated for a fixed time period. The TC826

signal integration period is 20 clock periods or counts.

The externally set clock frequency is divided by 32

before clocking the internal counters. The integration

time period is:

EQUATION 4-1:

FIGURE 4-1:

TC826 ANALOG SECTION

Where:

FOSC = External Clock Frequency

TSI =

FOSC

x20

DE-

DE+

DE-

–

Buffer

Comparator

Integrator

RINT

To Digital Section

CMPTR

REF IN

CAZ

CINT

VDD

INT

≈ VDD – 2.9V

+Input

Analog

Common

-INPUT

CREF

–

≈ VDD

INT

µA

VDD

≈ 6.3V

TC826

Analog Switch

From

Digital

Control

Center

INT

DE+

DE-

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