A13 datasheet(46/55 Pages) ETC2

46 / 55 page

Allwinner Technology CO., Ltd.

A13 Datasheet v1.30

December 10, 2012

18.

CIR Interface

18.1.

Overview

The CIR features:



Full physical layer implementation



Support CIR for remote control or wireless keyboard



Dual 8x16-bit FIFO for data transfer



Programmable FIFO thresholds



Support Interrupt and DMA

CIR receiver is implemented in hardware to save CPU resource. It samples the input signals on the

programble frequency and records these samples into RX FIFO when one CIR signal is found on

the air. The CIR receiver uses Run-Length Code (RLC) to encode pulse width, and the encoded

data is buffered in a 64 levels and 8-bit width RX FIFO: the MSB bit is used to record the polarity

of the receiving CIR signal (The high level is represented as 1 and the low level is represented as

0), and the rest 7 bits are used for the length of RLC. The maximum length is 128. If the duration

of one level (high or low) is more than 128, another byte is used. Since there are always some

noises in the air, a threshold can be set to filter the noises to reduce system loading and improve

system stability.

18.2.

CIR Controller Signal Description

Signal Name

Description

Type

IR_TX

CIR Transmit Data signal

IR_RX

CIR Receive Data signal

Table 18. CIR Controller Signal Description

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