ML4804

12

diode for this function, it is important to limit the current

through the Zener to avoid overheating or destroying it.

This can be easily done with a single resistor in series

with the Vcc pin, returned to a bias supply of typically

18V to 20V. The resistor’s value must be chosen to meet

the operating current requirement of the ML4804 itself

(8.5mA, max.) plus the current required by the two gate

driver outputs.

EXAMPLE:

driving a total gate charge of 90nC at 100kHz (e.g., 1

IRF840 MOSFET and 2 IRF820 MOSFETs), the gate driver

current required is:

IkHz

nC

mA

=

100

90

9

(7)

R

VV

II

Iz

BIAS

BIAS

CC

CC

G

=

−

++

(8)

R

VV

mA

mA

mAIz

−

++

=

20

15

69

5

250Ω

The ML4804 should be locally bypassed with a 1.0µF

ceramic capacitor. In most applications, an electrolytic

capacitor of between 47µF and 220µF is also required

across the part, both for filtering and as part of the start-up

bootstrap circuitry.

LEADING/TRAILING MODULATION

Conventional Pulse Width Modulation (PWM) techniques

employ trailing edge modulation in which the switch will

turn on right after the trailing edge of the system clock.

The error amplifier output voltage is then compared with

the modulating ramp. When the modulating ramp reaches

the level of the error amplifier output voltage, the switch

will be turned OFF. When the switch is ON, the inductor

current will ramp up. The effective duty cycle of the

trailing edge modulation is determined during the ON

time of the switch. Figure 4 shows a typical trailing edge

control scheme.

In the case of leading edge modulation, the switch is

turned OFF right at the leading edge of the system clock.

When the modulating ramp reaches the level of the error

amplifier output voltage, the switch will be turned ON.

The effective duty-cycle of the leading edge modulation

is determined during the OFF time of the switch. Figure 5

shows a leading edge control scheme.

One of the advantages of this control technique is that it

requires only one system clock. Switch 1 (SW1) turns off

and switch 2 (SW2) turns on at the same instant to

minimize the momentary “no-load” period, thus lowering

ripple voltage generated by the switching action. With

such synchronized switching, the ripple voltage of the

first stage is reduced. Calculation and evaluation have

shown that the 120Hz component of the PFC’s output

ripple voltage can be reduced by as much as 30% using

this method.

TYPICAL APPLICATIONS

Figure 6 is the application circuit for a complete 100W

power factor corrected power supply, designed using the

methods and general topology detailed in Application

Note 33.

Figure 5. Typical Leading Edge Control Scheme

REF

EA

–

+

–

+

OSC

DFF

R

D

Q

Q

CLK

U1

RAMP

CLK

U4

U3

C1

RL

I4

SW2

SW1

+

DC

I1

I2

I3

VIN

L1

VEAO

CMP

U2

RAMP

VEAO

TIME

VSW1

TIME