ML4819

7

SLOPE COMPENSATION

Slope compensation is accomplished by adding 1/2 of the

current flowing out of pin 12 to pin 1 (for the PFC section

and pin 9 (for the PWM section). The amount of slope

the impedance to GND on pin 1 or pin 9. Since most of

the PWM applications will be limited to 50% duty cycle,

slope compensation should not be needed for the PWM

section. This can be defeated by using a low impedance

load to the current sense on pin 9.

500

400

300

200

100

0

0

100

200

300

400

500

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V

1. 5V

SINE INPUT CURRENT (µA)

Figure 8. Gain Modulator Linearity

ENABLE

GEN.

9V

INTERNAL

BIAS

–

+

Figure 9. Under-Voltage Lockout Block Diagram

40

30

20

10

0

0

102030

40

Figure 10a. Total Supply Current vs. Supply Voltage

START-UP

25

30

35

20

15

10

5

0

0

1020

30405060

70

TEMPERATURE ( C)

OPERATING

CURRENT

OSC

10

20

12

TO PIN 9

TO PIN 1

9V

RAMP COMP

SLOPE

COMPENSATION

Q1

Figure 7. Slope Compensation Circuit

UNDER VOLTAGE LOCKOUT

On power-up the ML4819 remains in the UVLO condition;

output low and quiescent current low. The IC becomes

below 10V, the UVLO condition is imposed. During the

usable as a status flag.