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ML4828CS 데이터시트(PDF) 6 Page - Micro Linear Corporation

부품명 ML4828CS
상세설명  BiCMOS Phase Modulation/Soft Switching Controller
PDF  11 Pages
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제조업체  MICRO-LINEAR [Micro Linear Corporation]
홈페이지  http://www.microlinear.com
Logo MICRO-LINEAR - Micro Linear Corporation

ML4828CS 데이터시트(HTML) 6 Page - Micro Linear Corporation

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6
ML4828
SETTING THE OSCILLATOR FREQUENCY
The ML4828 switching frequency is determined by the
charge and discharge times of the network connected to
the RT and CT pins. Figure 3 shows the relationships
between the internal clock and the charge and discharge
times.
tDISCHARGE
RAMP PEAK
RAMP VALLEY
tCHARGE
2.5V
1.25V
INTERNAL
CLOCK
Figure 3. Internal Oscillator Timing.
The frequency of the oscillator is:
f
tt
OSC
CHARGE
DISCHARGE
=
+
1
(1)
The ramp peak is 2.5V and the ramp valley is 1.25V,
giving a ramp range of 1.25V. The charging current is set
externally through the resistor RT:
I
V
R
CHARGE
T
= 25
.
(2)
while the discharging current is fixed at 1.4 mA. The
charge and discharge times can be determined by:
t
CV
I
CR
CHARGE
T
CHARGE
TT
=
×
=
×
125
2
.
(3)
t
CV
I
CV
mA
DISCHARGE
T
DISCHARGE
T
=
×
=
×
125
1 25
14
..
.
(4)
The oscillator frequency can then be found by substituting
the results of equations 3 and 4 into equation 1. This
frequency activates a T flip-flop which generates the
output pulses. The T flip-flop acts as a frequency divider
(
÷2), so the output frequency will be:
f
f
OUT
OSC
=
2
(5)
ERROR AMPLIFIER
The ML4828 error amplifier has a 10MHz bandwidth and
a 10V/
µs slew rate. Figure 4 gives the Bode plot of the
error amplifier.
100
80
60
40
20
0
–20
180
135
90
45
0
100
1K
10K
100K
1M
10M
100M
FREQUENCY
GAIN
PHASE
Figure 4. Error Amplifier Open-Loop Gain
and Phase vs. Frequency.
OUTPUT DRIVERS
The ML4828 has four high-current CMOS output drivers,
each capable of 1A peak output current. These outputs
have been designed to quickly switch the gates of power
MOSFET transistors via a gate drive transformer. For higher
power applications, the outputs can be connected to
external MOSFET drivers.
The output phase delay times are set by charging an
internal 6.7pF capacitor up to the REF voltage (2.5V) via a
current that is externally programmed through RA and RB,
for the side A and side B drivers, respectively. The
charging current and delay time for side A are given by:
I
V
R
A
A
= 25
.
(6)
tpF R
DA
A
67
.
(7)
The same equations can be applied to RB. For example,
with RA = 33kΩ:
tpF
k
ns
DA
Ω =
6 7
33
220
.
(8)



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