전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

AR0230CSSC00SUEA0-DRBR 데이터시트(PDF) 31 Page - ON Semiconductor

부품명 AR0230CSSC00SUEA0-DRBR
상세설명  Full HD Digital Image Sensor
PDF  36 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  ONSEMI [ON Semiconductor]
홈페이지  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

AR0230CSSC00SUEA0-DRBR 데이터시트(HTML) 31 Page - ON Semiconductor

Back Button AR0230CSSC00SUEA0-DRBR Datasheet HTML 27Page - ON Semiconductor AR0230CSSC00SUEA0-DRBR Datasheet HTML 28Page - ON Semiconductor AR0230CSSC00SUEA0-DRBR Datasheet HTML 29Page - ON Semiconductor AR0230CSSC00SUEA0-DRBR Datasheet HTML 30Page - ON Semiconductor AR0230CSSC00SUEA0-DRBR Datasheet HTML 31Page - ON Semiconductor AR0230CSSC00SUEA0-DRBR Datasheet HTML 32Page - ON Semiconductor AR0230CSSC00SUEA0-DRBR Datasheet HTML 33Page - ON Semiconductor AR0230CSSC00SUEA0-DRBR Datasheet HTML 34Page - ON Semiconductor AR0230CSSC00SUEA0-DRBR Datasheet HTML 35Page - ON Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 31 / 36 page
background image
AR0230CS/D Rev. 8, Pub. 11/15 EN
31
©Semiconductor Components Industries, LLC, 2015.
AR0230CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor
Power-On Reset and Standby Timing
Power-On Reset and Standby Timing
Power-Up Sequence
The recommended power-up sequence for the AR0230CS is shown in Figure 11. The
available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have
the separation specified below.
1. Turn on VDD_PLL power supply.
2. After 100s, turn on VAA and VAA_PIX power supply.
3. After 100s, turn on VDD_IO power supply.
4. After 100s, turn on VDD power supply.
5. After 100s, turn on VDD_SLVS power supply.
6. After the last power supply is stable, enable EXTCLK.
7. Assert RESET_BAR for at least 1ms. The parallel interface will be tri-stated during this
time.
8. Wait 150000 EXTCLKs (for internal initialization into software standby.
9. Configure PLL, output, and image settings to desired values.
10. Wait 1ms for the PLL to lock.
11. Set streaming mode (R0x301a[2] = 1).
Figure 11:
Power Up
VDD_PLL (2.8)
VAA_PIX
VAA (2.8)
VDD_IO (1.8/2.8)
VDD (1.8)
VDD_SLVS (0.4)
EXTCLK
RESET_BAR
t0
t1
t2
t3
tx
t4
t5
t6
Hard Reset
Internal
Initialization
Software
Standby
PLL Lock
Streaming



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com