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AR0330 데이터시트(PDF) 31 Page - ON Semiconductor

부품명 AR0330
상세설명  CMOS Digital Image Sensor
PDF  77 Pages
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AR0330_DS Rev. U Pub. 4/15 EN
31
©Semiconductor Components Industries, LLC,2015.
AR0330: 1/3-Inch CMOS Digital Image Sensor
HiSPi Transmitter
Cycle-to-cycle jitter (tCYCJIT) is defined as the difference in time between consecutive
clock high and clock low periods tHCLK and tLCLK, quoting the RMS value of the variation
(tHCLK - tLCLK).
If pk-pk jitter is also measured, this should be limited to ±3-sigma.
Notes:
1. One UI is defined as the normalized mean time between one edge and the following edge of the
clock.
2. Taken from the 0 V crossing point with the DLL off.
3. Also defined with a maximum loading capacitance of 10pF on any pin. The loading capacitance
may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum
0.3 UI.
4. The absolute mean skew between the clock lane and any data lane in the same PHY between any
edges.
5. The absolute mean skew between any clock in one PHY and any data lane in any other PHY
between any edges.
6. Differential skew is defined as the skew between complementary outputs. It is measured as the
absolute time between the two complementary edges at mean VCM point. Note that differential
skew also is related to the VCM_AC spec which also must not be exceeded.
Table 24:
HiVCM Electrical AC Specification
Parameter
Symbol
Min
Max
Unit
Notes
Data Rate
1/UI
280
700
Mbps
1
Bitrate Period
tPW
1.43
3.57
ns
1
Max setup time from transmitter
tPRE
0.3
UI
1, 2
Max hold time from transmitter
tPOST
0.3
UI
1, 2
Eye Width
tEYE
0.6
UI
1, 2
Data Total Jitter (pk-pk) @1e-9
tTOTALJIT
0.2
UI
1, 2
Clock Period Jitter (RMS)
tCKJIT
50
ps
2
Clock Cycle-to-Cycle Jitter (RMS)
tCYCJIT
100
ps
2
Rise time (20% - 80%)
tR
150ps
0.3
UI
3
Fall time (20% - 80%)
tF
150ps
0.3
UI
3
Clock duty cycle
DCYC
45
55
%
2
Clock to Data Skew
tCHSKEW
-0.1
0.1
UI
1, 4
PHY-to-PHY Skew
tPHYSKEW
2.1
UI
1, 5
Mean differential skew
tDIFFSKEW
-100
100
ps
6



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